Modern computer systems often have many devices or nodes linked together by a common bus. These devices establish communication by one device being the sending node and a second device being the receiving node. Control lines and protocols enable the data transfer to occur over the common bus between the pair of devices.
Asynchronous data transfer systems in the prior art include the Unibus, SCSI, and FIPS channel. In these asynchronous systems, each device or node has a set of rules depending on its role and its role is based on its function. Thus a host processor is usually the master and a memory is a slave. After some prior arbitration, addressing and selection process, the master identifies a device with whom it will communicate. The master will assert a specific or dedicated control line and place the data on the common bus. The slave which has a separate control line then responds over the common bus. Release of both dedicated control lines means the data has been transferred. For a limited number of devices, this system is acceptable. However, as devices are added to or taken from the system, a number of lengthy processes must be performed to account for the changes in the system.
In yet another known prior art system for performing asynchronous data transfers, multiple sending nodes and/or multiple receiving nodes are contemplated. Each node has its own separate control line for sending and for receiving data. Obviously the more nodes in the system, the greater the number of control lines and the more complex the system becomes.
As systems become more flexible and devices have more intelligence and multiple functions, the need for multiple sending and/or receiving nodes in the computer system increases. What is needed is a generalized data transfer system. Ideally this system will be symmetrical and provide for a minimum of control signals while maximizing the throughput of the system.